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GENLINX II TM GS9000D
Serial Digital Decoder
DATA SHEET FEATURES * fully compatible with SMPTE 259M-ABC * decodes 8 and 10 bit serial digital signals for data rates to 270Mb/s * recommended alternative to GS9000C for use when interfacing directly to GS7025, GS9025A or GS9035A * incorporates automatic standards selection * 325mW power dissipation at 270MHz clock rate * Pb-free and Green * operates from single +5 or -5 volt supply * 28 pin PLCC packaging APPLICATIONS * * 4SC and 4:2:2 serial digital interfaces The GS9000D is packaged in a 28 pin PLCC and operates Automatic standards select controller for serial routing and distribution applications from a single 5 volt, 5% power supply. Differential pseudo-ECL inputs for both serial clock and data are internally level shifted to CMOS levels. Digital outputs such as parallel data, parallel clock, HSYNC, Sync Warning and Standard Select are all TTL compatible. DEVICE DESCRIPTION The GS9000D is a CMOS integrated circuit specifically designed to deserialize SMPTE 259M serial digital signals at data rates up to 270Mb/s. The GS9000D is a pin and functional equivalent to the GS9000C, with the exception of SDI input levels which are compatible for direct interfacing to the GS7025, GS9025A and GS9035A. The device incorporates a descrambler, serial to parallel convertor, sync processing unit, sync warning unit and automatic standards select circuitry.
GS9000D
ORDERING INFORMATION
PART NUMBER GS9000DCPJ GS9000DCTJ GS9000DCPJE3 GS9000DCTJE3 PACKAGE 28 Pin PLCC 28 Pin PLCC Tape 28 Pin PLCC 28 Pin PLCC Tape TEMPERATURE 0C to 70C 0C to 70C 0C to 70C 0C to 70C Pb-FREE AND GREEN No No Yes Yes
GS9000D
SERIAL DATA IN SERIAL DATA IN LEVEL SHIFT 30 - BIT SHIFT REG PARALLEL DATA OUT (10 BITS)
DESCRAMBLER
SP
SERIAL CLOCK IN SERIAL CLOCK IN
LEVEL SHIFT
SCLK
SYNC DETECT (3FF 000 000 HEX) Sync
Word Boundary
PARALLEL TIMING GENERATOR
PARALLEL CLOCK OUT
SYNC CORRECTION ENABLE
SYNC CORRECTION Sync Error HSYNC OUTPUT
SYNC WARNING CONTROL
SYNC WARNING (Schmitt Trigger Comparator) AUTO STANDARD SELECT
SYNC WARNING FLAG
STANDARDS SELECT CONTROL
OSC
2 BIT COUNTER Hsync Reset
SS0 SS1
FUNCTIONAL BLOCK DIAGRAM
Revision Date: June 2004 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 18784 - 3
ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage (VS = VDD - VSS) Input Voltage Range (any input) DC Input Current (any one input) Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 10 seconds) VALUE 7V -0.3 to (VDD + 0.3) 10A 0C to 70C -65C to +150C 260C
GS9000D
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, TA = 0C to 70C unless otherwise shown
PARAMETER Supply Voltage Power Consumption (outputs unloaded) CMOS Input Voltage
SYMBOL VS PC
CONDITIONS Operating range = 143MHz = 270MHz
MIN 4.75 3.4 -
TYP 5.00 235 325 4.5 0.2 -
MAX 5.25 1.5 0.5 10
UNITS V mW mW V V V V A
NOTES
TEST LEVEL 3 7 7 1 1 1 1 3
VIHMIN VILMAX
TA = 25C
Output Voltage
VOHMIN VOLMAX
IOH = 4mA, 25C IOL = 4mA, 25C VIN = VDD or VSS
2.4 -
Input Leakage Current Serial Clock and Data Inputs Common Mode Voltage
IN
VCM
TA = 25C, VIN = 700 to 1200mVpp
3.0
-
4.05
V
Centre of Swing
1
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test.
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AC ELECTRICAL CHARACTERISTICS
VDD = 5V, TA = 0C to 70C unless otherwise shown
PARAMETER Serial Input Clock Frequency Serial Input Data Rate Serial Data and Clock Inputs: Setup Hold Signal Swing Parallel Clock: Jitter Parallel Data: Risetime and Falltime
SYMBOL SCI DRSDI
CONDITIONS
MIN 100 100
TYP -
MAX 270 270
UNITS MHz Mb/s
NOTES
TEST LEVEL 1 1
GS9000D
TA = 25C tSU tHOLD VIN tJCLK tR-PDn TA = 25 TA = 25C, CL = 10pF 1.0 1.0 700 800 1.0 3 1200 ns ns mVpp ns p-p ns 20% to 80% Rising edge of PCLK to bit period centre 7 7 1 7 7
PDn to PCLK Delay Tolerance
tD
-
-
3
ns
7
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test.
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VSS
SWF
VSS
HSYNC
(MSB) PD9
PD8
VSS
4 SDI 5
3
2
28
27
26 25 PD7
GS9000D
SDI
6
24
PD6
SCI
7
23
PD5
GS9000D
SCI 8
TOP VIEW
22
PD4
SS1
9
21
PD3
SS0
10
20
PD2
SSC
11 12 13 14 15 16 17 18
19
PD1
VDD
VDD
SCE
SWC
PCLK
PD0 (LSB)
VDD
Fig. 1 GS9000D Pin Outs, 28 Pin PLCC Package
PIN DESCRIPTIONS
PIN NO. 1 2 3 SYMBOL HSYNC VSS SWF Output TYPE Output DESCRIPTION Horizontal Sync Output. CMOS (TTL compatible) output that toggles for each TRS detected. Power Supply. Most negative power supply connection. Sync Error Warning Flag. CMOS (TTL compatible) active high output that indicates the preselected HSYNC Error Rate (HER). The HER is set with an RC time constant on the SWC input. Power Supply. Most negative power supply connection. Inputs Inputs Output Input Differential, pseudo-ECL serial data inputs. ECL voltage levels with offset of 3.0V to 4.05V for operation up to 270MHz. See AC Electrical Characteristics Table for details. Differential, pseudo-ECL serial clock inputs. ECL voltage levels with offset of 3.0V to 4.05V for operation up to 270MHz. See AC Electrical Characteristics Table for details. Standard Select Outputs. CMOS (TTL compatible) outputs is generated by a 2-bit internal binary counter which stops cycling when a valid TRS is detected by the GS9000D. Standards Select Control. Analog input used to set a time constant for the standards select hunt period. An external RC sets the time constant. Power Supply. Most positive power supply connection. Power Supply. Most positive power supply connection. Input Sync Correction Enable. Active high CMOS input which enables sync correction by not resetting the GS9000D's internal parallel timing on the first sync error. If the next incoming sync is in error, internal parallel timing will be reset. This is to guard against spurious HSYNC errors. When SCE is low, a valid sync will always reset the GS9000D's parallel timing generator
4 5, 6 7, 8 9,10 11 12 13 14
VSS SDI/SDI SCI/SCI SS1/SS0 SSC VDD VDD SCE
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PIN DESCRIPTIONS
PIN NO. 15 16 17 18 19-25 26 27 28 SYMBOL SWC PCLK PD0 VDD PD1 - PD7 VSS PD8 PD9 Output Output Outputs TYPE Input Output Output DESCRIPTION Sync Warning Control. Analog input used to set the HSYNC Error Rate (HER). This is accomplished by an external RC time constant connected to this pin. Parallel Clock Output. CMOS (TTL compatible) clock output where the rising edge of the clock is located at the centre of the parallel data window within a given tolerance. See Fig. 7. Parallel Data Output - Bit 0 (LSB). CMOS (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing the least significant bit (LSB). Power Supply. Most positive power supply connection. Parallel Data Outputs - Bit 1 to Bit 7. CMOS (TTL compatible) descrambled parallel data outputs from the serial to parallel convertor representing data bit 1 through data bit 7. Power Supply. Most negative power supply connection. Parallel Data Output. CMOS (TTL compatible) descrambled parallel data output from the serial to parallel convertor representing data bit 8. Parallel Data Output - Bit 9 (MSB). CMOS (TTL compatible) descrambled data output from the serial to parallel convertor representing the most significant bit (MSB).
GS9000D
INPUT/OUTPUT CIRCUITS
VDD
VDD
VDD
REXT SSC SDI SCI
EXTERNAL COMPONENTS VDD
BIAS
Fig. 2 Pin 11 SSC
SDI SCI
VDD VDD
Fig. 4 Pins 5 - 8 SDI - SCI
SCE
Fig. 3 Pin 14 SCE
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VDD
VDD
VDD
REXT SWC 6k8 CEXT EXTERNAL COMPONENTS
GND
OUTPUT
GS9000D
Fig. 5 Pin 15 SWC
Fig. 6 Pins 3, 16, 17, 19 - 25, 27, 28 SWF, HSYNC, SSI, SSD, PCLK, PD0-9
tCLKL = tCLKH
1/ T 2
1/
2T
SERIAL CLOCK (SCI)
50%
PARALLEL DATA (PDn)
SERIAL DATA (SDI)
PARALLEL CLOCK (PCLK)
50%
tSU
tHOLD
Fig. 7 Waveforms
tD
TEST SET-UP & APPLICATION INFORMATION Figure 8 shows the test set-up for the GS9000D operating from a VDD supply of +5 volts. The differential pseudo ECL inputs for DATA and CLOCK (pins 5,6,7 and 8) must be biased between +3.0 and +4.05 volts. In the application circuit shown in Figure 11, these inputs can be directly driven from the outputs of the GS7025 Reclocking Receiver with their resistor values set as shown. In other cases, such as true ECL level driver outputs, two biasing resistors are needed on the DATA and CLOCK inputs and the signals must be AC coupled. It is critical that the decoupling capacitors connected to pins 12,13 and 18 are chip types and are located as close as possible to the device pins. The critical high speed inputs, such as Serial Data (pins 5 and 6) and Serial Clock (pins 7 and 8), are located along one side of the device package to maintain very short interconnections when interfacing with the GS7025 Receiver.
If the automatic standard select function is not used, the Standard Select bits (pins 9 and 10) do not need to be connected, however the control input (pin 11) should be grounded.
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+5V
22 3 x 100n
** Locate the three 0.10F decoupling capacitors as close as possible to the corresponding pins on the GS9000D. Chip capacitors are recommended.
HSYNC OUTPUT
1 VDD VDD VDD HSYNC 17 PD0 DECODER 19 PDI 5 SDI GS9000D 20 PD2 6 SDI 21 PD3 7 SCI PD4 22 8 SCI 23 PD5 9 SS1 24 PD6 10 SS0 PD7 25 11 SSC PD8 27 PD9 28 PCLK SCE VSS VSS VSS SWC SWF 2 4 26 15 3 10p 13 x 425 39k 16 14 ** 12 13 18
PARALLEL DATA BIT 0 PARALLEL DATA BIT 1 PARALLEL DATA BIT 2 PARALLEL DATA BIT 3 PARALLEL DATA BIT 4 PARALLEL DATA BIT 5 PARALLEL DATA BIT 6 PARALLEL DATA BIT 7 PARALLEL DATA BIT 8 PARALLEL DATA BIT 9 PARALLEL CLOCK OUT SYNC CORRECTION ENABLE
GS9000D
SDIIN SDIIN SCIIN SCIIN
STANDARDS SELECT BIT 1 STANDARDS SELECT BIT 0
+5V 100k 820p
SYNC WARNING FLAG
+5V
All resistors in ohms, all capacitors in farads, unless otherwise specified.
Fig. 8 GS9000D Test Set-Up
With synchronized serial data and clock connected to the GS9000D, the HSYNC output (pin 1) will toggle for each HSYNC detected. The Parallel Data bits PD0 through PD9 and the Parallel Clock can be observed on an oscilloscope or fed to a logic analyzer. To directly drive parallel inputs to receiving equipment, such as monitors or digital to analog converters, these outputs can be fed through a suitable TTL to ECL converter. In operation, the HSYNC output from the GS9000D decoder toggles on each occurrence of the timing reference signal (TRS). The state of the HSYNC output is not significant, but the time at which it toggles is significant.
4SC DATA STREAM HSYNC OUT 4:2:2 DATA STREAM HSYNC OUT T R S ACTIVE VIDEO & H BLANKING T R S ACTIVE VIDEO & H BLANKING T R S
The HSYNC output toggles to indicate the presence of the TRS on the falling edge of PCLK, one data symbol prior to the output of the first word in the TRS. In the following diagram, data is indicated in 10-bit Hex.
PCLK
PDN
XXX 3FF 000 000 XXX
XXX 3FF 000 000 XXX
HSYNC
Fig. 10 Operation of HSYNC with Respect to PCLK
E A V
H BLNK
S A V
ACTIVE VIDEO
E A V
H BLNK
S A V
Fig. 9 Operation of HSYNC Output
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TYPICAL APPLICATION CIRCUIT - Adjustment Free Multi-standard Serial To Parallel Convertor
Vcc 8.2nH Serial Data Output 1uF 75 100nF 1uF Vcc 100nF
90.9
90.9
GS9000D
75
Vcc
SDO 37.5 SDO VEE RSET
VCC SDI SDI VEE
1 GS9028 2
8 7
100nF
Vcc 150 LOCK Vcc
3 4
Vcc
6 5
59 4.75k
Vcc CLK_EN 150
22k
Vcc 150
CD
CLK_EN
Vcc
Vcc 100nF
3k3
100
4.7nF
Vcc
OEM_TEST
CLK_EN
SSI/CD
COSC
LOCK
Vcc
MOD
VCC
VEE
VEE
44 DDI 1 2 3 4 5 6 7 8 9 10 11 12 100k Pot
VCC
A/D
HSYNC
100
SWF
VSS
VSS
VSS
PD8
PD9
43
42
41
40
39
38
37
36
35
34 33 32 31 30 VEE SDO SDO VEE SCO SCO VEE NC Vcc NC
90.9
90.9
100 100 100 100 100 100 100 100 100 Vcc
4 SDI SDI SCI SCI SS1 SS0 SSC 5 6 7 8 9 10 11 12
3
2
1
28
27
26 25 24 23 PD7 PD6 PD5 PD4 PD3 PD2 PD1
100nF
Serial Data Input
Vcc
DDI VCC_75 VCC
Vcc
(1) Typical value for input return loss matching (2) The GS7025 can be replaced by either the GS9025A or GS9035A for applications at data rates less then 270Mb/s or when equalization is not required
GS9000D and GS7025 INTERCONNECTIONS Figure 11 shows an application of the GS9000D in a 270Mb/s serial to parallel converter. This circuit uses the GS7025 Serial Digital Receiver. For datarates below 270Mb/s the GS9025A can be used. If cable equalization is not required the GS7025 or GS9025A may be replaced with a GS9035A Reclocker IC. The GS9028 Cable Equalizer allows a serial loop through after the reclocker.
GENNUM CORPORATION
75 100nF 15nH (1)
37.5 75 10n 75 Vcc 10n
VEE SDI SDI VCC VEE
GS7025 (2)
29 28 27 26 25 24 23
GS9000D
22 21 20 19
Vcc 270 NC
13
14
15
16
17
18
100nF 100nF
VDD
VDD
PD0
PCLK
SWC
SCE
VDD
CD_ADJ AGC-
100nF
100
100nF
13
14
15
16
17
18
19
20
21
22
Vcc
RVCO_RTN
VEE
LF-
LFS
LF+
VEE
VCC
AGC+
CBG
VCC
RVCO 365
100nF
1.8k 15nF
Vcc
100nF
100pF Vcc
68k *
22nF
3.3pF
NOTE: Value of SDO and SCO pull-up resistors is 90.9 1%
Fig. 11
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SYNC WARNING FLAG OPERATION Each time HSYNC is not correctly detected, the Sync Warning Flag output (pin 3 ) will go HIGH. The RC network connected to the Sync Warning Control input (pin 15) sets the number of sync errors that will cause the SWF pin to go HIGH. The component values of the RC network shown in Figure 12 set the SWF error rate to approximately one HSYNC error in 10 lines. These component values are chosen for optimum performance of the SWF pin, and should not be adjusted. Typically, HSYNC errors become visible on a monitor before the SWF provides an indication of HSYNC errors. As a result, the SWF function can be used in applications where the detection of significant signal degradation is desired. A high SWF goes low when the input error rate decreases below the set rate. A small amount of hysteris in the comparator ensures noise immunity.
VDD
GS9000D
15 SYNC WARNING CONTROL
COMPARATOR
VDD 6k8
3
+
SYNC WARNING FLAG (SWF)
SYNC ERROR
Fig. 12 Sync Warning Flag Circuit
CAUTION
ELECTROSTATIC SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION
DOCUMENT IDENTIFICATION
PRELIMINARY DATA SHEET The product is in a preproduction phase and specifications are subject to change without notice.
REVISION NOTES: Added lead-free and green information.
GENNUM CORPORATION
MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5
GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F 6-14-1, Nishi Shinjuku Shinjuku-ku, Tokyo 160-0023 Japan Tel: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523
Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright May 2000 Gennum Corporation. All rights reserved. Printed in Canada.
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